1. Field of the Invention
The present invention relates to a boot up of computer systems and in particular to an intelligent endpoint coupled to the computer systems that can manage aspects of the boot up.
2. Description of the Related Art
When a computer is turned on, a central processing unit (CPU) of the computer must “boot up”. This boot up (also called a boot) of the computer loads a limited number of predetermined programs into the system memory. These programs advantageously provide the basic tools and utilities that define the initial operations of the computer system, e.g. initialization, diagnostics, and operating system loading.
The instruction code for triggering the boot up is often stored in non-volatile memory of the computer. Non-volatile cells can store bit states, i.e. 0's and 1's, even in the event of a power outage. The instruction code (bootcode) is sometimes in the form of firmware.
In one embodiment, the boot up firmware can be implemented in a type of electrically erasable non-volatile memory called electrically erasable programmable read only memory (EEPROM). In certain configurations, the EEPROM cells in an array can be simultaneously erased, and therefore are also called “flash” memory. Recently, the cost and power requirements of flash memory have been significantly reduced in a per bit base by the introduction of NAND flash memory. Influenced by this introduction, flash memory (NAND and other types of flash memory) is increasingly being used in computers for boot up firmware.
An industry standard called the peripheral connect interface (PCI) has been developed to efficiently use a bus to connect peripherals to a host platform, e.g. a computer. To address certain limitations in PCI, another industry standard called PCI Express has recently been jointly developed by Intel Corporation and the PCI Special Interest Group (PCI-SIG). PCI Express (PCI-XP) is a serial, low voltage, self-clocking I/O transfer methodology. PCI-XP typically outperforms PCI in high-speed applications but maintains backwards compatibility with PCI. Compared with PCI, PCI-XP improves data reliability and fault tolerance, thereby resulting in better reliability, availability, and serviceability (RAS).
FIG. 1 illustrates an exemplary PCI Express system that includes two computer systems, wherein each computer system is coupled to a plurality of peripherals, called endpoints herein. A first computer system 100 includes a CPU 101, a cache 102, and a platform memory 103. A second computer system 120 includes a CPU 112, a cache 113, and a platform memory 114.
Each computer system can further include a root complex and one or more switches associated with its input/output (I/O) system. A root complex is the “root” of the connection of an I/O system of the computer to its memory. Thus, a root complex 104 connects CPU 101 and memory 103. Similarly, root complex 115 connects CPU 112 and memory 114.
Each root complex is connectable to a plurality of endpoints via one or more switches. Both root complexes and switches are controlled by their associated computers. In a PCI Express system, an endpoint is a peripheral device that can request and complete PCI transactions either for itself or on behalf of a non-PCI Express device (e.g. a legacy device). A switch can be used to direct traffic in a PCI Express hierarchy including multiple endpoints.
For example, for root complex 104, a switch 105 can direct traffic to/from endpoint 106, a switch 107 can direct traffic to/from endpoint 108, and switches 107 and 109 can direct traffic to/from endpoints 110 and 111. Similarly, for root complex 115, a switch 116 can direct traffic to/from endpoint 120 and switches 116 and 117 can direct traffic to/from endpoints 118 and 119. In FIG. 1, a peer-to-peer link 130 can also be established between switches 107 and 116, thereby supporting transactions between hierarchy domains. These endpoints, switches, and peer-to-peer link form the “fabric” of the computer systems.
Conventional boots in FIG. 1 are controlled by booting platforms in computer systems 100 and 120 (e.g. in the CPUs and memories). Due to peer-to-peer link 130, some coordination may be desired between the boots of computer systems 100 and 120. Typically, a system administrator manually provides this coordination, thereby adding expense and unpredictability to the combined system. Alternatively, each booting platform could include additional instructions for dealing with the arbitration between computer systems 100 and 120. These additional instructions are very complex, thereby significantly increasing the size and computing resources of each of the booting platforms. Therefore, a need arises for an automatic, efficient boot of computer systems having a peer-to-peer link.